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femtoclocks? crystal-to-lvds clock generator ics844008i-46 idt ? / ics ? lvds clock generator 1 ics844008aki-46 rev. a may 19, 2008 g eneral d escription the ics844008i-46 is a 10gb ethernet clock generator and a member of the hipercloc ks? f amily of high performance devices from idt. the ics844008i-46 can synthesize 156.25mhz or 100mhz with a 25mhz crystal. it has a total of 8 lvds outputs. the ics844008i-46 has excellent phase jitter performance and is packaged in a 32 lead vfqfn package , making it ideal for use in systems with limited board space. f eatures ? eight differential lvds outputs ? crystal oscillator interface designed for 18pf parallel resonant crystals ? supports the following output frequencies: 156.25mhz or 100mhz ? vco frequency: 625mhz or 600mhz ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.45ps (typical) ? full 2.5v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packages hiperclocks? ic s p in a ssignment phase detector vco 625mhz or 600mhz fb = 25 or 24 osc q0:q7 nq0:nq7 xtal_in xtal_out freq_sel oe pulldown pullup 25mhz 4 or 6 8 8 b lock d iagram 24 23 22 21 20 19 18 17 nc oe gnd nq7 q7 v ddo nq6 q6 q0 nq0 gnd q1 nq1 v ddo q2 nq2 q3 nq3 gnd q4 nq4 v ddo q5 nq5 v dda freq_sel v dd nc nc xtal_in xtal_out gnd ics844008i-46 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 f requency s elect f unction t able t u p n i r e d i v i d b fr e d i v i d t u p t u o) z h m ( o c v y c n e u q e r f t u p t u o ) z h m ( y c n e u q e r f l a t x ) z h m (l e s _ q e r f 5 205 2 4 5 2 6) t l u a f e d ( 5 2 . 6 5 1 5 214 2 6 0 0 60 0 1
idt ? / ics ? lvds clock generator 2 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k t able 3. oe f unction t able s t u p n i e o s t u p t u o ] 7 : 0 [ q n / ] 7 : 0 [ q 1) t l u a f e d ( d e l b a n e 0z - i h r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 3 , 2 2 , 1 1 , 3d n gr e w o p. d n u o r g y l p p u s r e w o p 5 , 41 q n , 1 qt u p u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 9 1 , 4 1 , 6v o d d r e w o p. s n i p y l p p u s t u p t u o 8 , 72 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 0 1 , 93 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 14 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 6 1 , 5 15 q n , 5 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 16 q n , 6 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 27 q n , 7 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 3 2e ot u p n ip u l l u p . h g i h n e h w . d e l b a s i d e r a s t u p t u o , w o l n e h w . n i p e l b a n e t u p t u o . 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o 9 2 , 8 2 , 4 2c nd e s u n u. t c e n n o c o n 5 2v a d d r e w o p. n i p y l p p u s g o l a n a 6 2l e s _ q e r ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 7 2v d d r e w o p. n i p y l p p u s e r o c , 0 3 1 3 , n i _ l a t x t u o _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? lvds clock generator 3 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) contin uous current 10ma surge current 15ma package thermal impedance, ja 37c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i e ov d d v = n i 5 2 6 . 2 =5a l e s _ q e r fv d d v = n i 5 2 6 . 2 =0 5 1a i l i t n e r r u c w o l t u p n i e ov d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a l e s _ q e r fv d d v , v 5 2 6 . 2 = n i v 0 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a d d e g a t l o v y l p p u s g o l a n av d d 5 2 . 0 ?5 . 2v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 6a m i a d d t n e r r u c y l p p u s g o l a n a 5 2a m i o d d t n e r r u c y l p p u s t u p t u o 0 4 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 7 4 20 4 34 5 4v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 0 1 . 15 2 . 15 7 3 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m t able 4c. lvds dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c
idt ? / ics ? lvds clock generator 4 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 0 0 3w . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 6. ac c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 = l e s _ q e r f5 2 . 6 5 1z h m 1 = l e s _ q e r f0 0 1z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 5 7s p t ) c c ( t i jr e t t i j e l c y c - o t - e l c y c 0 2s p t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 3 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 . 6 5 15 4 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 0 0 12 5 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 7s p c d oe l c y c y t u d t u p t u o 8 42 5% . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 3 e t o n
idt ? / ics ? lvds clock generator 5 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator t ypical p hase n oise at 156.25mh z 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.45ps (typical) o ffset f requency (h z ) dbc hz n oise p ower ? ethernet filter ? raw phase noise data ? phase noise result by adding ethernet filter to raw data t ypical p hase n oise at 100mh z o ffset f requency (h z ) 100mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.52ps (typical) ? 10gb ethernet filter ? raw phase noise data ? phase noise result by adding a 10gb ethernet filter to raw data
idt ? / ics ? lvds clock generator 6 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator p arameter m easurement i nformation rms p hase j itter 2.5v lvds o utput l oad ac t est c ircuit t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power o utput s kew c ycle - to -c ycle j itter scope qx nqx 2.5v5% power supply +? float gnd lvds o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles q0:nq7 nq0:nq7 v dda v dd, v ddo t pw t period t pw t period odc = x 100% q0:q7 nq0:nq7 20% 80% 80% 20% t r t f v od q0:q7 nq0:nq7
idt ? / ics ? lvds clock generator 7 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator d ifferential o utput v oltage s etup o ffset v oltage s etup out out lvds dc input ? ? ? v os / v os v dd ? ? ? 100 out out lv d s dc input v od / v od v dd p arameter m easurement i nformation , continued a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the ics844008i-46 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 2.5v .01 f v dd
idt ? / ics ? lvds clock generator 8 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator c rystal i nput i nterface the ics844008i-46 has been characterized with an 18pf parallel resonant crystals. the capacitor values shown in f igure 2. c rystal i npu t i nterface figure 2 below were determined using a 25mhz parallel resonant crystal and were chosen to minimize the ppm error. f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _i n xta l _o u t .1uf rs xtal_in xtal_out x1 18pf parallel crystal c1 27p c2 27p i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds o utputs all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, there should be no trace attached.
idt ? / ics ? lvds clock generator 9 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator 2.5v lvds d river t ermination figure 5 shows a typical termination for lvds driver in characteristic impedance of 100 differential (50 single) transmission line environment. f igure 5. t ypical lvds d river t ermination 2. 5v 100 ohm differential transmission line 2. 5v lvds_driv er r1 100 + - 100 differential transmission line f igure 4. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p at h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base pac kage, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? lvds clock generator 10 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator s chematic l ayout figure 6 shows an example of ics844008i-46 application schematic. in this example, the device is operated at v dd = v ddo = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 27pf are recommended to logic input pins c4 10uf nq2 oe r1 10 nq4 vddo set logic input to '0' to logic input pins freq_sel zo = 50 ohm zo = 50 ohm r4 50 nq7 q7 q6 nq0 c1 27pf rd2 1k nq6 vdd= vddo=3.3v vdd q7 nq1 q3 r2 100 x1 25mhz vdd vddo gnd nq3 q4 ru2 not install + - vddo c2 27pf c9 0.1uf set logic input to '1' zo = 50 ohm logic control input examples r3 50 c3 0.01u q5 vdda nq5 nq6 q1 c7 0.1uf rd1 not install q2 ru1 1k c5 0.1uf zo = 50 ohm q6 c8 0.1uf vdd nq7 18pf q0 vdd + - u1 ics844008i-46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 q0 nq0 gnd q1 nq1 vddo q2 nq2 q3 nq3 gnd q4 nq4 vddo q5 nq5 q6 nq6 vddo q7 nq7 gnd oe nc gnd xtal_out xtal_in nc nc vdd freq_sel vdda c6 0.1uf alternate lvds termination for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built- in termination are shown in this schematic. f igure 6. ics844008i-46 s chematic l ayout
idt ? / ics ? lvds clock generator 11 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics844008i-46. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844008i-46 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max + i ddo_max ) = 2.625v * (60ma + 25ma + 140ma) = 590.625mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.591w * 37c/w = 106.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 32-l ead vfqfn, f orced c onvection ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? lvds clock generator 12 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator r eliability i nformation t ransistor c ount the transistor count for ics844008i-46 is: 2993 t able 8. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? lvds clock generator 13 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator p ackage o utline - k s uffix for 32 l ead vfqfn t able 9. p ackage d imensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9 below. n o i t a i r a v c e d e j ) 4 - / 2 - d h h v ( s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 2 3 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 8 n e 8 e , d c i s a b 0 . 5 2 e , 2 d 0 . 33 . 3 l 0 3 . 00 5 . 0
idt ? / ics ? lvds clock generator 14 ics844008aki-46 rev. a may 19, 2008 ics844008i-46 femtoclocks? crystal-to-lvds clock generator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t f l 6 4 - i k a 8 0 0 4 4 8l 6 4 i a 8 0 0 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 6 4 - i k a 8 0 0 4 4 8l 6 4 i a 8 0 0 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ics844008i-46 femtoclocks? crystal-to-lvds clock generator innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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